Passive Release does is allow the write buffer to independently write the data to the PCI bus at the first available opportunity. It can do so even when the processor is busy doing something else.
Without Passive Release, the write buffer waits till the CPU reasserts the write request before it writes to the PCI bus. This still saves time (and improves performance) because the CPU doesn't actually need to resend the data. The write buffer is ready to offload the data the moment the PCI bus arbiter releases control of the bus to the CPU. However, because the write buffer has to wait for the CPU to retry the transaction, this reduces its effectiveness.
This is a particularly big problem when an ISA device engages the ISA bus. Because the ISA bus is very slow, this ties up the PCI bus and prevents the CPU from accessing it for a very long time. If the CPU-to-PCI write buffer had been enabled, the CPU immediately writes to the buffer. This frees the CPU to engage in other tasks but the write buffer cannot write to the PCI bus until both the CPU is free to retry the write and the PCI bus is free to receive.
Passive Release helps by allowing the write buffer to "passively write" to the PCI bus without CPU intervention and while the ISA device is engaging the PCI bus. This essentially allows the CPU to indirectly write to the PCI bus even when the ISA device has control over it. Without this feature, the PCI bus arbiter will only allow other (non-CPU) PCI masters to access the PCI bus.